1. Field of the Invention
The present invention relates to an automatic wiring method for a semiconductor integrated circuit, a program for the same, and a semiconductor integrated circuit, and, more particularly, to an automatic wiring method for a semiconductor integrated circuit suitable for use in designing a cell-based IC, which is one type of ASIC (Application Specific Integrated Circuit), having macrocells registered in a library and laid out on an IC chip, to a program for the same, and to a semiconductor integrated circuit designed by means of this type of automatic wiring method for a semiconductor integrated circuit.
2. Description of a Related Art
Recent development of higher-level integration and higher density system design in semiconductor integrated circuits, such as large-scale integrated circuits (LSI), very large-scale integrated circuits (VLSI), and ultra large-scale integrated circuits (ULSI), has allowed an integrated circuit having over one million transistors. One example is a system LSI, in which a system composed of a central processing device (CPU), a storage device (ROM, RAM), a buffer, and a plurality of peripheral devices and the like for processing various signals are connected by a bus, signal line, or the like, and the system is built into a single semiconductor chip.
Because of the large circuit size of this type of system LSI, transistor-level circuit design cannot be performed directly, and system design, functional design, detailed logical design, and circuit design must be performed in sequential stepwise fashion.
In the system design, the operation and structure of the system as a whole are determined so as to render the CPU, ROM, RAM, buffer, and plurality of peripheral devices each as a single functional block to obtain the desired function. In the functional design, the relationship between functional blocks and the internal operation of the functional blocks are determined based on the specifications determined in the system design. In the detailed logical design, a simulation model of the semiconductor integrated circuit is created by laying out macrocells for constituting the functional blocks whose operation was determined by the above-mentioned functional design on an IC chip, and interconnecting (arranging and wiring) these components.
The above-mentioned macrocells are composed of NAND gates, NOR gates, or other basic logical elements, as well as latches, counters, memory, or other basic logical circuits made up of a combination of the aforementioned gates. The above-mentioned macrocells are registered as a library in which their functions are described using Hardware Description Language (HDL), C-language (registered trademark), or another programming language.
The semiconductor integrated circuit simulation model thus created is compiled along with the macrocell library, a simulation of the operation thereof is carried out, and verification is performed for verifying whether or not the desired function will be obtained.
In the circuit design, the transistor-level electronic circuit and element characteristics are determined so as to satisfy the circuit specification based on the logical design consisting of the functional design and detailed logical design.
Computer simulation of the circuit operation and verification are also performed in design stages other than the logical design.
FIG. 18 is an overhead schematic view of a macrocell constituting a cell-based IC designed by the conventional semiconductor integrated circuit design method (logical design) and the periphery thereof, and FIGS. 19 and 20 are process diagrams for describing the same design method.
As depicted in FIGS. 18 and 19, the macrocell in this example has rectangular power terminals 2a and 2b, ground terminals 3a and 3b, a plurality of input/output terminals 4, 4, and so on formed on the edge of the core 1. The rectangular power terminals 2a and 2b and ground terminals 3a and 3b are formed in the third layer inside the core unit 1, and connected to the longitudinal power line and longitudinal ground line arranged in the fourth layer.
The substantially rectangular frame formed by the boundary of the rim of the core 1 or the extension thereof and the straight line obtained by connecting the leading ends of the plurality of input/output terminals 4, 4, and so on formed at the lower edge of the core 1 is referred to as a macro outer frame 5, and the orbital power ring 6 is formed so as to enclose the macro outer frame 5 in the vicinity of the macro outer frame 5.
This semiconductor integrated circuit design method is executed by means of a design support program stored in the storage unit of a design support device being processed by a controller having a CPU.
First, the above-mentioned controller positions the macrocell in the desired location on the chip on the basis of chip data and macrocell data read from the storage unit.
The rectangular power terminals 2a and 2b and ground terminals 3a and 3b constituting the line pattern are then placed on the third layer inside the core 1 as depicted in FIG. 19.
The above-mentioned controller reads the information stored in the storage unit for the chip internal power line composed of the transverse ground bus 7 and transverse power bus 8 in a pair lined in the fifth layer, and when the transverse ground bus 7 and transverse power bus 8 are present near the macro outer frame 5 in the placement setting area of a given width from the top of the macro outer frame 5 upward and from the bottom thereof downward, these components are set as the transverse power line and transverse ground line constituting a quasi-orbital power ring 6, as depicted in the same figure.
When placement of additional transverse power line or transverse ground line is possible in the above-mentioned placement setting area above and below the transverse ground bus 7 and transverse power bus 8 constituting the orbital power ring 6, the above-mentioned controller also adds and places independent transverse ground line 9 (12) or transverse power line 11 (13) as depicted in the same figure.
The above-mentioned controller then lines longitudinal power line 14 (16) and longitudinal ground line 15 (17) in a pair in the fourth layer inside the placement setting area of a given width that contains the left and right sides of the macro outer frame 5 as depicted in the same figure.
The above-mentioned controller then connects the longitudinal ground line 15 and 17, the transverse ground line 9 and 12, and the transverse ground bus 7 by a via-hole, and connects the longitudinal power line 14 and 16, the transverse power line 11 and 13, and the transverse power bus 8 by a via-hole.
The above-mentioned controller then performs terminal processing of the chip internal power line. Specifically, the above-mentioned controller connects and terminates the terminal longitudinal ground bus 18a with the transverse ground line 9 through the via-hole. The terminal longitudinal ground bus 18b and transverse ground line 12 are also connected and terminated through the via-hole. The above-mentioned controller also connects and terminates the terminal longitudinal power bus 18c with the transverse power line 11 through the via-hole, and connects and terminates the terminal longitudinal power bus 18d and transverse power line 13 through the via-hole.
The above-mentioned controller also connects and terminates the ground follow pin 18e with the longitudinal ground line 15 through the via-hole, and connects and terminates the ground follow pin 18f with the longitudinal ground line 17 through the via-hole. The above-mentioned controller also connects and terminates the power follow pin 18g with the longitudinal power line 14 through the via-hole, and connects and terminates the power follow pin 18h with the longitudinal power line 16 through the via-hole.
The above-mentioned controller then connects the orbital power ring 6 with the power terminals 2a and 2b and ground terminals 3a and 3b placed in the third layer of the macrocell. Specifically, the above-mentioned controller then places the longitudinal power line 19a and longitudinal ground line 19b in straight lines in the fourth layer over a section that starts at the upper transverse power line 11 and transverse ground line 9 that constitute the orbital power ring 6, passes directly over the power terminals 2a and 2b and ground terminals 3a and 3b, and extends all the way to the lower transverse power line 13 and transverse ground line 12 in the extending direction, as depicted in FIG. 20.
In this arrangement, via-holes are formed at the locations at which the longitudinal power line 19a and longitudinal ground line 19b overlap with the power terminals 2a and 2b and ground terminals 3a and 3b, and respective connections are made through the via-holes between the longitudinal power line 19a and the power terminals 2a and 2b, and between the longitudinal ground line 19b and the ground terminals 3a and 3b. 
With the above-mentioned controller, the transverse ground bus 20a and transverse power bus 20b, which are formed in the fifth layer and made to pass over the core 1, are then connected with the longitudinal power line 14, 16, and 19a and with the longitudinal ground line 15, 17, and 19b, respectively, through the via-holes at the intersection points thereof as depicted in FIG. 18; a mesh-shaped power line structure is formed for maintaining the given power supply capability; and the sequence of processing is completed.
By means of this configuration, the structure of the macrocell and the power line connection method can be determined independent of the board information possessed by the semiconductor chip, particularly, the power line information. Even when other macrocells are formed above and below or to the left or right of the macrocell, a stable power supply can be provided without current dissipation or local voltage drop.
A technique is also proposed for providing a stable power supply independent of the layout or the like of the power line, whereby the power line of the macrocell is connected with the power line of the semiconductor chip via a power terminal (see Japanese Unexamined Patent Application Publication No. 2001-338982, for example). In this technique too, for example, a configuration is adopted whereby the power line and power terminal of the macrocell are connected via a through-hole.
However, the above-mentioned technique has drawbacks in that a large number of through-holes must be formed in order to connect the power terminals and ground terminals with the longitudinal power line and longitudinal ground line placed on a separate line layer, a long time is taken to generate position information and other information about as many through-holes as there are connection points, and the amount of calculation increases, thereby increasing the overall time required for the wiring process.
Drawbacks also exist whereby the size of the data to be stored increases because of the need to define and store in the storage unit location information about all of the power terminals and ground terminals in order to connect each of the power terminals and ground terminals with the longitudinal power line and longitudinal ground line.
Consequently, drawbacks also occur whereby the time taken to read the data in the wiring process increases, and the number of steps increases. Too much processing time is required particularly in such cases as when a large number of power terminals are in scattered positions.
Drawbacks occur when an orbital power ring is formed outside the macrocell, whereby the space occupied by the orbital power ring becomes large and the density of macrocells mounted on the semiconductor chip is reduced, thus creating an obstacle to the miniaturization of the surface area of the semiconductor chip.
Drawbacks also occur whereby the circuit pattern formed in the core 1 is formed only in the third or lower line layer, for example, in which the power terminals and ground terminals are formed, and the area in which no longitudinal power line or longitudinal ground line is placed in the fourth layer, in which the longitudinal power line and longitudinal ground line connected with the power terminals and ground terminals through the via-holes are placed, becomes unusable, wasted space. Because of this, drawbacks occur whereby the surface area of the macrocell increases, and the latitude of design flexibility is reduced.